A 100–750 MS/s 11-Bit Time-to-Digital Converter With Cyclic-Coupled Ring Oscillator

This paper presents the first measured cyclic-coupled ring oscillator (CCRO) time-to-digital converter (TDC). The CCRO realizes a robust true time-domain delay interpolation with sub-gate-delay resolution. architecture employs real-time quantization to reduce conversion time and hence maximize bandwidth. Furthermore, phase progression is encoded bubble error suppression logic, thereby building resilience mismatches from circuit/layout imperfections. prototype circuit implemented in 28 nm CMOS process demonstrates combination of high resolution sample rate over wide range rates. TDC achieves its peak figure-of-merit (FoM) 0.051 pJ/conv.-step at 100 MS/s while delivering 8.38-bit linear 15.4 ps resolution, operating 0.55 V supply. highest reported 9.29 bits among converters above MS/s, 125 0.9 supply, achieving 4.4 0.16 FoM. Further, quantizing allows fast operation up 750 where delivers 6-bit 0.48 FoM